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| Name | Last modified | Size |
|---|---|---|---|
| Parent Directory | - | |
| Nacrt.pdf | 2017-11-10 16:30 | 66K |
| Nacrt-h.odg | 2017-11-10 16:30 | 27K |
| Nacrt.odg | 2017-11-10 16:30 | 28K |
| orodje.txt | 2017-11-10 16:30 | 86 |
| Year2013Volume13_02_10.pdf | 2017-11-10 16:30 | 2.1M |
| Thesis_rhee.pdf | 2017-11-10 16:30 | 1.4M |
| swra029.pdf | 2017-11-10 16:30 | 6.5M |
| Stabilnost.png | 2017-11-10 16:30 | 123K |
| Stabilnost.bmp | 2017-11-10 16:30 | 1.1M |
| PLL_tutorial_slides.pdf | 2017-11-10 16:30 | 4.2M |
| PLL_intro_594a_s05.pdf | 2017-11-10 16:30 | 463K |
| PLLTutorialISSCC2004.ppt | 2017-11-10 16:30 | 861K |
| PLLm.pcb | 2017-11-10 16:30 | 171K |
| PLLm.BAK | 2017-11-10 16:30 | 171K |
| PLLm.1.pcb | 2017-11-10 16:30 | 163K |
| pll70a.png | 2017-11-10 16:30 | 39K |
| PLL2.odp | 2017-11-10 16:30 | 25K |
| PLL1.pdf | 2017-11-10 16:30 | 88K |
| PLL.png | 2017-11-10 16:30 | 87K |
| PLL.pdf | 2017-11-10 16:30 | 96K |
| PLL.pcb | 2017-11-10 16:30 | 171K |
| PLL.odp | 2017-11-10 16:30 | 167K |
| PLL.odg | 2017-11-10 16:30 | 165K |
| PLL.BAK | 2017-11-10 16:30 | 171K |
| PLL.1.pcb | 2017-11-10 16:30 | 163K |
| Phase Locked Loop Design Fundamentals.pdf | 2017-11-10 16:30 | 410K |
| MT-086.pdf | 2017-11-10 16:30 | 407K |
| choi_jaehyouk_201012_phd.pdf | 2017-11-10 16:30 | 1.3M |
| AN-30.pdf | 2017-11-10 16:30 | 185K |
| A multiple modulator fractional divider1.pdf | 2017-11-10 16:30 | 519K |
| 21991-47265.pdf | 2017-11-10 16:30 | 125K |
| 01530920.pdf | 2017-11-10 16:30 | 142K |